There are a PDP (plasma display panel) and a liquid crystal panel etc. as dot matrix display panels, and I/P (interlace-to-progressive) conversion, scanning line conversion, horizontal pixel conversion and vertical frequency conversion can be listed as signal processing techniques necessary and inevitable for these display panels.
I/P conversion is processing of converting an interlace signal to a progressive signal. Scanning line conversion is processing of performing vertical expansion processing and reduction of a display image. Horizontal pixel conversion is processing of performing horizontal expansion and reduction of a display image. Each conversion of these is a technique necessary and inevitable for a dot matrix display device having fixed numbers of horizontal and vertical pixels.
Vertical frequency conversion is processing of converting the vertical frequency of a video signal to a vertical frequency suitable to the display device, and it is most desirable to set the vertical frequency to 60 Hz due to limitation of a gradation representation technique in the PDP and due to limitation of the gradation representation technique and the operating speed thereof in the liquid crystal panel. When the vertical frequency of the video signal is larger than 60 Hz, therefore, a vertical frequency conversion processing circuit converting this vertical frequency to 60 Hz is extremely useful.
As a conventional video signal conversion device performing the aforementioned I/P conversion, there is a scanning line conversion circuit disclosed in Japanese Patent Laying-Open Gazette No. 7-123367, for example. FIG. 35 is a circuit diagram showing the structure of the conventional scanning line conversion circuit, and FIG. 36 is a diagram showing filter coefficients of the scanning line conversion circuit shown in FIG. 35.
The scanning line conversion circuit shown in FIG. 35 synthesizes an interpolation line of a current field from data of precedent and subsequent fields and data of the current field. First, a luminance signal supplied to an input terminal 331 is supplied to a first high-pass filter 330. The first high-pass filter 330 has a pair of cascade-connected delay means 332 and 333 having a delay time of 1 H (H: horizontal scanning period), and luminance signals on input/output stages thereof are synthesized in an adder 337 through corresponding coefficient units 334, 335 and 336.
As respective coefficients of the coefficient units 334 to 336, coefficients shown in FIG. 36 are employed. Referring to FIG. 36, the transverse direction thereof corresponds to the fields and the vertical direction shows the vertical direction V in the fields. The illustrated filter coefficients are set for respective lines of the same fields. In the scanning line conversion circuit shown in FIG. 35, therefore, the coefficient of the coefficient unit 335 corresponding to the actual lines is 6/24, and those of the upper and lower coefficient units 334 and 336 are −3/24. Amplifiers can be used for the coefficients 334 to 336, and the upper and lower coefficient units 334 and 336 present inverter structures as illustrated when amplifiers are used.
The luminance signal delayed by 2 H is supplied to delay means 360 of 260 H in order to obtain a delay time substantially corresponding to one field, so that the luminance signal supplied to the input terminal 336 is output exactly with a delay of one field. This luminance signal delayed by one field is supplied to a low-pass filter 340.
The low-pass filter 340 supplies filter characteristics on the basis of data of seven lines as shown in FIG. 36. Therefore, the low-pass filter 340 has three cascade-connected delay means 341 to 343 having a delay time of 1 H, and respective input/output signals are multiplied by prescribed coefficients by corresponding coefficient units 344 to 347 and thereafter synthesized in an adder 348. The luminance signal output from the delay means 341 is used as a luminance signal L1 in a current line, and this is supplied to a changeover switch 366. For the low-pass filter 340, a filter coefficient of 2/24 is selected with respect to first and seventh lines, and a filter coefficient of 10/24 is selected with respect to third and fifth lines, as shown in FIG. 36.
The luminance signal further delayed by 3H by the low-pass filter 340 is supplied to a second high-pass filter 350 through delay means 362 of 260 H. By providing the delay means 362, it follows that the luminance signal supplied to the input terminal 331 is delayed by two fields. The luminance signal delayed by two fields is supplied with a prescribed high-pass characteristic in this second high-pass filter 350, the structure of which is similar to that of the first high-pass filter 330.
An output of an adder 356 is further supplied to an adder 364, so that respective filter outputs are synthesized. Thus, when the fourth line of the subsequent field and the fourth line of the precedent field are present between the third line and the fifth line of the current field, the interpolation line therebetween is obtained by adding outputs of the high-pass filters for three lines each of the precedent and subsequent fields and outputs of the low-pass filter for four lines of the current fields by the adder 364.
As a conventional video signal conversion device performing scanning line conversion and horizontal pixel conversion, there is an image processor disclosed in Japanese Patent Laying-Open Gazette No. 10-134175, for example. FIG. 37 is a block diagram showing the structure of the conventional image processor.
A remainder circuit 305 outputs the decimal part of the sum of a phase change Pd supplied from a prescribed device and the value of a register 302 to the register 302. An approximation circuit 303 outputs a filter signal Pi whose phase x corresponds to a filter coefficient set corresponding to a phase most approximate to the value of the register 302 to a coefficient memory 400. Thus, an optimum filter coefficient set is selected from a prescribed number of filter coefficient sets in interpolation of prescribed pixel data. According to Cubic approximation, product-sum operation of four filter coefficient sets thereof and four pixel data is performed by multipliers 405 to 408 and an adder 409, interpolation values of pixels are calculated and expansion or reduction of an image in an arbitrary conversion ratio can be performed.
As hereinaove described, detailed disclosure is made in relation to individual conversion such as I/P conversion, scanning line conversion, horizontal pixel conversion or the like in the conventional device, while no report has been made as to a device systematically combining I/P conversion, scanning line conversion, horizontal pixel conversion and vertical frequency conversion but it is impossible to perform aforementioned each conversion by a single device and convert a video signal to a video signal suitable to a display device performing matrix display.